The present invention relates generally to a semiconductor integrated circuit, and more particularly to a delay locked loop (DLL) circuit used for a semiconductor integrated circuit and a method of controlling the same.
A conventional semiconductor integrated circuit synchronizes output data signals with an internal clock signal thereby improving the operating speed thereof. To synchronize the output data signals with the internal clock the conventional semiconductor integrated circuit includes a clock generator such as a DLL circuit. Recent design trends in the semiconductor industry include the increase in operation speeds of semiconductor integrated circuits. As the semiconductor integrated circuit continues to operate at higher speeds, technology for subdividing a phase of the internal clock signal to generate a multiphase internal clock signal and synchronizing data signals with each phase has been developed. With the development of such technology, the DLL circuit is implemented as a multiphase DLL circuit. Presently, a DLL clock signal is realized as a plurality of clocks having predetermined phase differences each other.
The conventional multiphase DLL circuit is implemented as an analog type and controls a phase of the DLL clock signal by supplying a control voltage obtained through a voltage pumping operation to a delay line. In the conventional multiphase DLL circuit a short locking time is required. When the locking time of the conventional multiphase DLL circuit is long, the plural clock signals in the DLL clock signal, which must have phase differences obtained by equally dividing one period of the DLL clock signal, are subject to errors such, e.g., harmonic lock or sub-harmonic lock, resulting in the plural clock signals in the DLL clock signal having phase differences obtained by equally dividing two or more periods of the DLL clock signal. In order to prevent such errors, the control voltage must have a proper level in an initial operation of the multiphase DLL circuit. However, the conventional multiphase DLL circuit has not been provided with a technical configuration capable of controlling the level of the control voltage in the initial operation. Thus, a multiphase DLL clock signal may not be stably operated.